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Memory Hierarchy and Access Time - Sand, Software Program And Sound
por Chiquita Bracewell (04-09-2025)
This page takes a more in-depth look on the Raspberry Pi memory hierarchy. Each stage of the memory hierarchy has a capability and pace. Capacities are comparatively easy to find by querying the working system or studying the ARM1176 technical reference manual. Velocity, however, will not be as easy to find and should often be measured. I exploit a easy pointer chasing method to characterize the conduct of every degree within the hierarchy. The method also reveals the conduct of memory-associated efficiency counter occasions at each level. The Raspberry Pi implements five levels in its Memory Wave Program hierarchy. The degrees are summarized in the desk below. The best stage consists of digital memory pages which can be maintained in secondary storage. Raspbian Wheezy retains its swap house within the file /var/swap on the SDHC card. That is sufficient house for 25,600 4KB pages. You might be allowed as many pages as will match into the preallocated swap space.
Our analysis beneath concentrates on the info cache. The info cache is 4-way set associative. Each way in an associative set shops a 32-byte cache line. The cache can handle as much as four energetic references to the identical set without battle. If all four ways in a set are valid and a fifth reference is made to the set, then a battle happens and one of many four ways is victimized to make room for the new reference. The data cache is nearly listed and physically tagged. Cache traces and tags are saved separately in DATARAM and TAGRAM, respectively. Digital deal with bits 11:5 index the TAGRAM and DATARAM. Given a 16KB capability, 32 byte strains and four methods, there have to be 128 sets. Virtual tackle bits 4:Zero are the offset into the cache line. The information MicroTLB interprets a virtual deal with to a physical tackle and sends the bodily deal with to the L1 information cache.
The L1 data cache compares the physical address with the tag and determines hit/miss status and the proper way. The load-to-use latency is three (3) cycles for an L1 knowledge cache hit. The BCM2835 implements a two degree translation lookaside buffer (TLB) structure for digital to physical handle translation. There are two MicroTLBs: a ten entry information MicroTLB and a ten entry instruction MicroTLB. The MicroTLBs are backed by the primary TLB (i.e., the second degree TLB). The MicroTLBs are absolutely associative. Each MicroTLB interprets a virtual tackle to a bodily handle in a single cycle when the page mapping info is resident within the MicroTLB (that is, a hit within the MicroTLB). The main TLB is a unified TLB that handles misses from the instruction and information MicroTLBs. A 64-entry, 2-approach associative construction. Main TLB misses are dealt with by a hardware page table walker. A page table stroll requires no less than one further memory access to seek out the web page mapping information in major memory.